Communications between integrated circuits (ICs) on a printed circuit board (PCB) or between ICs on different PCBs with a common backplane has conventionally used digital signaling, e.g., a level-sensitive binary protocol. For example, logic 0 is normally represented by a low voltage level, while logic 1 is represented by a high voltage level. A simplified example of such a system is shown in FIG. 1. FIG. 1 shows two ICs, i.e., IC 50 and IC 51. A simplified input/output buffer in each IC is shown (e.g., buffers 52-1 and 53-1). Expanded buffer 52-2 represents buffer 52-1 of IC 50 and expanded buffer 53-2 represents buffer 53-1 of IC 51. In FIG. 1, pad 56 is attached to an output buffer, i.e., output driver 60, and pad 57 attached to an input buffer 61 (note on actual pad would be attached to both an input buffer and an output driver). Output driver 60 delivers to pad 56 a signal having a high or a low voltage level, depending on the logic state of an input line 62. Pads 56 and 57 are connected by a metal trace 63 on a PCB.
Ideally input line 62 would have a voltage square wave with one of two voltage levels, having the output data, i.e., the logic 1's and 0s' from IC 50. The output data would go via output driver 60 to pad 56 and then travel via trace 63 to pad 57. The output data from IC 50 would then be input data to IC 51. The input data is buffered by input buffer 61 and goes to the rest of the IC 51 circuitry via output line 64.
As the speed of communications increases, e.g., in the gigahertz (GHz) range and above, the user of square waves with the amplitude having the data, starts to have significant bit error rate problems. One reason is that signal degradation, e.g., amplitude degradation and continuous phase shift, occur as a signal travels down a transmission line, e.g., trace 63. This signal degradation increases with the frequency of the signal. In addition, the fundamental and multiple harmonic frequencies that comprise a square wave undergo different phase shifts when propagating down a transmission line, i.e., dispersion occurs. These effects are exacerbated by the decreasing rise and fall times of the edges of the received square wave at, e.g., IC 51, that approximate the transmitted square wave at, e.g., IC 50. Hence the probability increases that the receiver will make a mistake in determining the logic levels of the received data.
Therefore there is a need in the high speed communication of data between IC's for an improved technique of signaling other than using binary amplitude changes on a square wave, i.e., binary digital signaling.